Embodiments of the present invention relate to circuits, and more particularly, to memory circuits.
As semiconductor process technology provides for smaller and smaller device size, sub-threshold leakage current in MOSFETs (Metal-Oxide-Semiconductor-Field-Effect-Transistor) may increase. Sub-threshold leakage current in a nMOSFET may occur when the gate-to-source voltage of the nMOSFET is less than its threshold voltage, VT. Sub-threshold leakage current may present design challenges for various on-chip memory structures, such as, for example, register files, CAMs (Content-Addressable-Memory), caches, SRAM (Static-Random-Access-Memory), and DRAM (Dynamic-RAM).
Shown in FIG. 1 is a portion of an on-chip SRAM, or cache memory. For simplicity, only four cells are indicated. The content of the stored data is read through complementary bit-lines 102 and 104 by sense amplifier 114. The cells are accessed by bringing one of word lines 106, 108, 110, and 112 HIGH. In the particular embodiment of FIG. 1, word line 106 is HIGH and word lines 108, 110, and 112 are LOW. By bringing word line 106, access nMOSFETs 116 and 118 are turned ON, and the state of memory element 120 may be sensed by sense amplifier 114 via bit-lines 102 and 104. The solid arrows nearby access nMOSFETs 116 and 118 indicate that conduction current flows through access nMOSFETs 116 and 118 to charge or discharge bit lines 102 and 104.
With word lines 108,110, 112 LOW, access nMOSFETs 121 are OFF because their gate-to-source voltages are less than their threshold voltages. However, there may be sub-threshold leakage current, as indicated by the dashed arrows nearby nMOSFETs 121. In the particular embodiment of FIG. 1, assume that memory element 120 is such that node 122 is HIGH, and memory elements 124 are such that nodes 126 are HIGH. Assume that bit-lines 102 and 104 are pre-charged to HIGH. When memory cell 120 is read, memory cell 120 will keep bit-line 102 HIGH and will bring bit-line 104 from HIGH to LOW. However, there will be contention with the sub-threshold leakage currents through access nMOSFETs 121, which try to charge bit-line 104 and discharge bit-line 102, opposite the effect of the conduction current through access nMOSFETs 116 and 118.
Shown in FIG. 2 is a portion of an on-chip register file. The state stored in memory element 202 is accessed by bringing read select line 204 HIGH so that pass nMOSFET 206 is ON, and keeping the other read select lines LOW. Assume that the state of memory element 202 is such that node 208 is LOW so that pass nMOSFET 210 is OFF. Assume that bit line 212 is pre-charged HIGH. Then, with read select line 204 brought HIGH, bit-line 212 will not be discharged by conduction current. However, there may be sub-threshold leakage current through pass nMOSFET 210 as indicated by the dashed arrow nearby nMOSFET 210. Assume also that nodes 214 are HIGH. Then, with read select lines 216 LOW, there may be sub-threshold leakage current flowing through pass nMOSFETs 218. Consequently, the sub-threshold leakage currents depicted in FIG. 2 will tend to discharge bit-line 212, and may increase the noise margin.
As seen above, sub-threshold leakage current in memory structures may cause undesired voltage level changes in bit-lines, which may lead to incorrect read operations. One approach to mitigating this problem is to partition the bit-lines so as to reduce the number of memory cells connected to any one bit-line. However, this leads to an increase in the number of sense amplifiers, which increases die area and may reduce performance.